The idea of 3D integration and connecting heterogeneous dices on a thin silicon interposer or stacking them on top of each other has become attractive to keep functional performance targets. 3D integration is a system-level architecture in which a chip is divided into a number of functional blocks, each block is placed on separate layer, or strata, and these strata are stacked and interconnected through the silicon or other semiconductor material, in the Z-direction. The main attribute of these structures is the Z axis interconnect called a “through silicon via”, or simply TSV. TSVs provide a high-density alternative to the conventional substrates found in MCMs and SiPs: shorter interconnects, better weight, size and power characteristics. That 3D TSV package provides in comparison with today’s package-on-package (PoP) solution 35% smaller package size, 50% lower power and 8x wider the bandwidth.
Author(s) Details:
Konstantin O. Petrosyants,
National Research University Higher School of Economics (Moscow Institute of Electronics and Mathematics), Moscow, Russia and Institute for Design Problems in Microelectronics, Russian Academy of Sciences, Moscow, Russia.
Nikita I. Ryabov,
National Research University Higher School of Economics (Moscow Institute of Electronics and Mathematics), Moscow, Russia.